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    Navigation: All forums > Cores > Message List > Message Post

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    From: "H. Peter Anvin" <hpa@z...>
    Date: Wed, 21 May 2003 11:45:35 -0700
    Subject: Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
    Top

    Charles Lepple wrote:
    >>
    >> Something I never understood. Isn't it a conflict of interest
    >> if the Professor tells his students to buy a book that he wrote ?
    >> I mean it could be total crap, and nobody would know ....
    > 
    > It's a courtesy to the professor to use the book. A somewhat idealistic
    > view is that local use of the textbook will help shake out any errors in
    > the examples. In reality, it forces the student to either question the
    > correctness of the information presented, or to just be lazy and hope
    > for a curve because nobody bothered to figure out what the professor
    > intended to say.
    > 
    > That's why some consider it "academic incest" to earn more than one or
    > two degrees from the same school-- using your example, you would
    > hopefully find out whether or not the book was "total crap" while
    > studying at another institution.
    > 
    
    On the other hand, it *does* have the advantage that the book will be
    typically be written to match the teaching style of the professor.  I
    had at least one class in which the professor spent more than half the
    time arguing against what the book said, using different terminology,
    and handing out completely illegible hand-written notes.  As you can
    imagine, the exams where written to his notes, not to the book.
    
    	-hpa
    
    
    
    

    ReferenceAuthor
    [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1Joachim
    Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1Rudolf Usselmann
    Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1=?UTF-8?B?Sm9hY2hpbSBTdHLDtm1iZXJnc29u?=
    Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1Rudolf Usselmann
    Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1Paul
    Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1Rudolf Usselmann
    Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1Todd Fleming
    Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1Rudolf Usselmann
    Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1Charles Lepple

     
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