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Message
From: Tom Hawkins <tom1@l...>
Date: Wed, 21 May 2003 10:38:58 -0500
Subject: [oc] Verilog vs VHDL vs Other
The V versus V debate has gone on ever since the birth of HDL and it
will continue to a "topic of discussion" (putting it mildly) for
years to come. Both languages have their strengths, but both are
also fundementally flawed.
Some evidence of this are the countless Perl scripts used to
manipulate and manage HDL code -- practically every design house has
a suite of custom tools for this purpose. There are several other
language extensions built to either aid in RTL construction or assist
in modeling. A short list includes:
ParaCore - http://www.dilloneng.com/paracore.shtml
RubyHDL - http://www.aracnet.com/~ptkwt/ruby_stuff/RHDL/index.shtml
MyHDL - http://jandecaluwe.com/Tools/MyHDL/Overview.shtml
JHDL - http://www.jhdl.org/
Lava - http://www.xilinx.com/labs/lava/
HDLmaker - http://www.polybus.com/hdlmaker/users_guide/
The main purpose of a language -- programing, hdl, or otherwise -- is
to ease the expression of design. If either Verilog or VHDL were
adequate, most of these hacks would not be necessary.
It's not the fault of either. Both languages are 20 years old. 20
years ago, they were excellent modeling languages. Then 15 years
ago, Synopsys Design Compiler came along and made them excellent
design languages. But today, Verilog and VHDL are having a hard time
keeping up with Moore's law.
So now, Accellera and Synopsys are cramming features in to Verilog in
an attempt to coupe with the growing pains. This may help in some
respect, but IMHO, Verilog-2001 already suffered from feature-bloat.
Verilog-2001 features are still missing from many tools, and if you
listen to the rhedoric between Synopsys and Cadence, the later may
not even support SystemVerilog.
A language does not have to be complex to be able to express complex
design. This was our motivator for Confluence. Even though the
syntax is 3X smaller than Verilog-1995, it's semantics (recursion,
first class functions and environments, etc) and declarative nature
allows design to scale very easily.
I would like to donate Confluence to the OpenCore community. Maybe
have the tools on the server side, so anyone could generate Verilog,
VHDL, and C from any Confluence open core. Any ideas?
Regards,
Tom
--
Tom Hawkins
Launchbird Design Systems, Inc.
952-200-3790
tom1@l...
http://www.launchbird.com/
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