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Message
From: Rudolf Usselmann <rudi@a...>
Date: 21 May 2003 09:57:43 +0700
Subject: Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
On Wed, 2003-05-21 at 03:39, Todd Fleming wrote:
>
> Hello! I've been lurking on this list for several weeks now and thought I'd
> poke my head up here. I graduated from Virginia Tech. Like most schools, VT
> taught VHDL at the time but not Verilog. Now that I experiment with FPGAs I
> use Verilog; for some reason I just like it better. I don't know about other
> schools, but I do know why VT taught VHDL. A couple of the professors were on
> the VHDL specification committee. They are also the ones who taught the
> courses and wrote the book we used. There's a definite advantage to this; the
Something I never understood. Isn't it a conflict of interest
if the Professor tells his students to buy a book that he wrote ?
I mean it could be total crap, and nobody would know ....
> professors were able to explain not just the how's, but also the why's of
> VHDL. I don't see it as a major problem that I prefer a language I learned on
> my own; the concepts are similar enough that it was worth taking the VHDL
> course when I was in school.
>
> Todd Fleming
> flemingcnc.com
>
>
--
rudi
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