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    Navigation: All forums > Cores > Message List > Message Post

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    From: Joachim Strömbergson<Joachim.Strombergson@I...>
    Date: Tue, 20 May 2003 16:17:12 +0200
    Subject: Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
    Top

    Aloha!
    
    Marco Antonio Simon Dal Poz wrote:
    > On 20 May 2003, Rudolf Usselmann wrote:
    > 
    > 
    >>>I'm new here. I see most of the projects are done in Verilog. Why Verilog?
    >>>Most school teach VHDL.... My university teach VHDL.
    >>>I really don't want to juggle two languages.
    >>
    >>You should ask your school (and the other schools you are
    >>referring too), most of the industry is using Verilog.
    >>Search the archives, I have posted a message a while back
    >>in which the Synopsys CEO makes a statement that VHDL is
    >>dead. Which is probably not quite true, but shows you that
    >>the industry is at least trying to steer in to one direction ...
    > 
    > AFAIK, the industry is trying to steer in the direction of discarding
    > Synopsys. Please, correct me if I am wrong...
    
    <rant>
    You are wrong. ;-)
    
    There are specific areas where Cadence, Mentor et al are big and dominate, but 
    for large parts of the ASIC design flow, Synopsys not only dominate but have 
    gained market share. This has both to do with the (so far) successful merger 
    with Avanti, but old Synopsys tools have in same cases increased market share 
    (where it is possible - for STA PrimeTime is basically alone anyways).
    
    If you don't trust me, please check John Cooleys trip reports for the latest 
    DAC and SNUG [1]. Yes, SNUG is a Synopsys event, but you can probably trust 
    your fellow engineers when it comes to the tool polls.
    
    One area *not* dominated by Synopsys is FPGAs. But it's a pretty slim market 
    in terms of money, and the free tool offerings from Xilinx and Altera are 
    eating away the margins from below.
    
    And when it comes to VHDL vs Verilog vs Superlog/System Verilog and SystemC, 
    if engineer like/disklike is a measure, Verilog will *continue* to dominate 
    for the next years and slowly be replaced by System Verilog. And, yes, forget 
    VHDL and SystemC.
    </rant>
    
    
    [1]
    DAC 2002 Trip Report - Massive amounts of info:
    http://www.deepchip.com/posts/dac02.shtml
    
    SNUG 2003 Trip Report - Great reading:
    http://deepchip.com/posts/snug03.shtml
    
    -- 
    Med vänlig hälsning, Yours
    
    Joachim Strömbergson - Alltid i harmonisk svängning.
    VP, Research & Development
    ----------------------------------------------------------------------
    InformAsic AB / Hugo Grauers gata 5B / SE-411 33 GÖTEBORG / Sweden
    Tel: +46 31 68 54 90  Fax: +46 31 68 54 91  Mobile: +46 733 75 97 02
    E-mail: joachim.strombergson@i...  Home: www.informasic.com
    ----------------------------------------------------------------------
    
    
    
    
    

    ReferenceAuthor
    Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1Marco Antonio Simon Dal Poz

    Follow upAuthor
    Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1Marco Antonio Simon Dal Poz
    Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1Shehryar Shaheen

     
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