OPENCORES.ORG

From: paul <paulw@m...>
Date: Tue, 20 May 2003 03:42:45 -0700
Subject: Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1

Hi

I'm new here. I see most of the projects are done in Verilog. Why Verilog?
Most school teach VHDL.... My university teach VHDL.
I really don't want to juggle two languages.

Reference Author

[oc] Verilog coding style for Open Cores-RTL - Case in point SHA1 Joachim

Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1 Rudolf Usselmann

Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1 =?UTF-8?B?Sm9hY2hpbSBTdHLDtm1iZXJnc29u?=

Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1 Rudolf Usselmann

Follow up Author

Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1 Rudolf Usselmann