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Message
From: Niclas Hedhman <niclas@h...>
Date: Mon, 28 Apr 2003 12:37:55 -0800
Subject: Re: [oc] Async reset: active high or active low?
On Saturday 26 April 2003 11:48 pm, Haytham Azmi wrote:
> 3- I think you can check for any microcontrolle datasheet
> you will see that the reset is active high .
Well, "most" microcontrollers' datasheet will show you that the chip-external
RESET is active-low. From a board design point of view, one wants all RESET
to be active at the same state, to avoid multiple RESET lines, and/or
inverters. A majority of non-CPU components also have an active-low RESET,
although there are numerous exceptions.
As Rudolf points out, internally it shouldn't matter. The external RESET
should disable all output buffers, hence any other spurious states during
powerification (new word?) is irrelevant.
Niclas
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