Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: lin.sheng@z...
Date: Wed, 23 Apr 2003 08:49:19 +0800
Subject: [oc] =?gb2312?B?tPC4tDogW29jXSBWSERMIFByb2Nlc3Mgc3RhdGVtZW50?=

It will remain the value before enable signal switches.
Sheng Lin









Hi,
i read some vhdl code of the opencore HDLC and now i have
a question regarding process stements and how the hardware looks
like.

..
proc1: process (txclk, rst_n)
variable state :STD_LOGIC

if rst_n = ??then
  state    := '0';
  signal1 := '0';
 elseif txclk'event and txclk = '1' then
  if enable = '1' then
      state    := '1';
      signal1 := '1';
  end if;
 end if;
end if;

What values have state, signal1
if the enable signal switches to '0' ?
There is no elseif statement for that !!
Thanks.