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Message
From: "sphuynh" <sphuynh@m...>
Date: Thu, 17 Apr 2003 13:18:01 -0600
Subject: RE: [oc] How to model capacitor in Verilog??
It's mostly used for gate/transistor level modeling with charge delay.
-----Original Message-----
From: kinysh asdf [mailto:kinysh@h...]
Sent: Thursday, April 17, 2003 11:40 AM
To: cores@o...
Subject: RE: [oc] How to model capacitor in Verilog??
What's the use of modeling a cap?
in verilog all is digital. a cap will only be treated as some delay for
signal.
bests
>From: sphuynh <sphuynh@m...>
>Reply-To: cores@o...
>To: "'cores@o...'" <cores@o...>
>Subject: RE: [oc] How to model capacitor in Verilog??
>Date: Wed, 16 Apr 2003 08:29:16 -0600
>
>I haven't use it yet but I believe that is correct usage.
>
>// Strength is large, medium, small
>// Decay with trise = 0, tfall = 1, tdecay = 9
>// trireg (strength) #(trise, tfall, tdecay) capacitor
>
>
>-----Original Message-----
>From: kokloon@h... [mailto:kokloon@h...]
>Sent: Wednesday, April 16, 2003 4:54 AM
>To: cores@o...
>Subject: [oc] How to model capacitor in Verilog??
>
>
>Hi all,
>
>I am trying to model a capacitor using standard Verilog, but
>I have no idea how to do it...
>
>Does anybody have any idea on this??
>Issit like this??
>
>trireg (large) #(0,1,9) capacitor
>
>Thanks,
>Kok Loon
>
>
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