|
Message
From: Niclas Hedhman <niclas@h...>
Date: Mon, 7 Apr 2003 15:26:17 +0800
Subject: Re: [oc] verilog to vhdl converter
On Friday 04 April 2003 18:15, John Sheahan wrote:
> I recently wrote a perl script for converting synthesizeable
> verilog to vhdl.
>
> It copes with most of the structures I use, but is bound to
> suffer when other styles are involved.
>
> Is there any interst is posting and assisting tweaking this?
> I'd like fragments of code it has trouble with, and the expected
> result (both if it works, and does not, for regression)
I don't know how many software programmers are lurking on this list, but I am
a rather competent Java/C/assembly programmer, and willing to put in some
time to help out. Perl is not my game, but I think I would be able to
translate to Java, and make a web service out of it (if interest).
Niclas
|
 |
Browse
