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From: John Sheahan <jrsheahan@o...>
Date: Fri, 4 Apr 2003 20:15:31 +1000
Subject: [oc] verilog to vhdl converter

Hi

I recently wrote a perl script for converting synthesizeable 
verilog to vhdl.

It copes with most of the structures I use, but is bound to 
suffer when other styles are involved.

Is there any interst is posting and assisting tweaking this?
I'd like fragments of code it has trouble with, and the expected 
result (both if it works, and does not, for regression)

john

Follow up	Author
Re: [oc] verilog to vhdl converter	Niclas Hedhman
Re: [oc] verilog to vhdl converter	Rudolf Usselmann