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Last updated projects We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) Z80 System on Chip   Updated on: 16-May-2008   VLM: 1466 System on chip, based on T80 core. Version 0.5-DE1 is designed for Altera DE1 development board. Version 0.5-S3E is the port for Diligent Spartan 3E. Both projects provide access to leds, switches, buttons, keyboard and vga. DE1 version hav...   Category :: SoC Dependencies :: Other cores Language :: VHDL Development status :: Production/Stable   OPB SPI Slave   Updated on: 15-May-2008   VLM: 369 The OPB SPI-Slave Core is full configurable and support DMA-Transfers to write or read data directly to a memory. The SPI-Slave receive/transmit Data to a SPI-Master, for example a DSP or processor. The SPI-Clock and OPB-Bus clocks are complete...   Category :: Communication controller Language :: VHDL License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable   Reed Solomon Encoder   Updated on: 14-May-2008   VLM: 585 Reed Solomon Encoder synthesizable IP core compatible with G709, DVB1, DVB2 standards. Implements (n, k) code where n-k = 16 ( 8 byte error correction capable code). The verilog is written in such a way as to be easily parameterized for differ...   Category :: ECC core Language :: Verilog Phaze :: Design done Development status :: Production/Stable   OpenRISC 1000   Updated on: 14-May-2008   VLM: 12592 OpenRISC 1000 is an architecture of a family of open source, synthesizable RISC microprocessor cores. It is a 32-bit load and store RISC architecture designed with emphasis on speed, compact instruction set and scalability. OpenRISC 1000 targets ...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: ASIC proven Standard :: Wishbone compliant core Development status :: Production/Stable   JOP: a Java Optimized Processor   Updated on: 13-May-2008   VLM: 1062 JOP is the implementation of the Java Virtual Machine (JVM) as concrete machine in hardware. The design is full synthesizable and fits in low-cost FPGA devices from Altera and Xilinx.   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   aeMB   Updated on: 11-May-2008   VLM: 872 A clean room implementation of an EDK3.2 binary compatible Microblaze processor core. It is FPGA proven and has been extensively simulated using Icarus Verilog 0.8.5 and GPLCVER 2.11a to confirm performance. Simulation code is compiled using GCC ...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   ZPU - the worlds smallest 32 bit CPU with GCC toolchain   Updated on: 09-May-2008   VLM: 3538 This is the worlds smallest 32 bit CPU with a GCC/GDB toolchain, operating systems support(eCos), simulator, etc. Multiple VHDL implementations available. BSD license, except for those pieces to the puzzle that already have another open so...   Category :: Microprocessor Language :: VHDL Phaze :: Design done Phaze :: FPGA proven Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   CF State Space Processor   Updated on: 08-May-2008   VLM: 308 Confluence generated state space processor for multivariable linear systems.   Category :: Microprocessor Development status :: Production/Stable   CF LDPC Decoder   Updated on: 08-May-2008   VLM: 265 Confluence generated low-density parity-check (LDPC) decoder.   Category :: ECC core Development status :: Production/Stable   CF Reconfigurable Computing Array   Updated on: 08-May-2008   VLM: 304 Confluence generated reconfigurable computing array.   Category :: Coprocessor Development status :: Production/Stable   CF FIR Filter   Updated on: 08-May-2008   VLM: 521 Confluence generated finite impulse response (FIR) filters.   Category :: DSP core Development status :: Production/Stable   CF Interleaver   Updated on: 08-May-2008   VLM: 204 Confluence generated memory interleavers.   Category :: Memory core Development status :: Production/Stable   CF Floating Point Multiplier   Updated on: 08-May-2008   VLM: 357 Confluence generated floating point multipliers.   Category :: Arithmetic core Development status :: Production/Stable   CF FFT   Updated on: 08-May-2008   VLM: 1151 Confluence generated FFTs (Fast Fourier Transforms).   Category :: Arithmetic core Development status :: Production/Stable