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Last created projects We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) nonrestoringsquareroot   Updated on: unknown   VLM: 14 Square root operation is hard to implement on FPGAs because of the complexity of the algorithms. In this project, I intend to implement a very simple single precision floating point square root algorithm on FPGA. It is low-cost iterative implemen...     Wishbone to NPI core   Updated on: unknown   VLM: 12 The core converts wishbone transaction to the NPI interface link.     EUS FS - Alice II - Embeddable Single Board Computer   Updated on: 30-Apr-2008   VLM: 387 EUS FS is an "open" system board designed for industrial control and data acquisition applications. It is equipped with a 32-bit CPU working @ 200MHz (Etrax FS), Xilinx's gate array (Spartan 3E) and support electronics.   Category :: Prototype board Phaze :: Design done Development status :: Production/Stable   NPI graphics controller   Updated on: unknown   VLM: 14 A MPMC4 NPI video frame buffer interface with configurable VGA controller.     H.264/AVC Baseline Decoder   Updated on: 06-May-2008   VLM: 1863 This is a full dedicated H.264/AVC baseline decoder. Currently it supports QCIF 30fps decoding at 1.5MHz. It contains several main building blocks, such as bitstream parsing, intra-prediction, inter-prediction, and deblocking filter. It was both ...   Category :: Video controller Language :: Verilog Phaze :: ASIC proven Phaze :: FPGA proven Development status :: Production/Stable   Z80 System on Chip   Updated on: 16-May-2008   VLM: 1486 System on chip, based on T80 core. Version 0.5-DE1 is designed for Altera DE1 development board. Version 0.5-S3E is the port for Diligent Spartan 3E. Both projects provide access to leds, switches, buttons, keyboard and vga. DE1 version hav...   Category :: SoC Dependencies :: Other cores Language :: VHDL Development status :: Production/Stable   cpu65c02_tc - 65C02 Processor Soft Core with accurate timing   Updated on: 12-Apr-2008   VLM: 50 The 65C02 is the upgraded version of the legendary R6502. cpu65c02_tc offers you an accurate timing for all new and upgraded op codes of the 65C02. This soft core was generated in VHDL and designed with Mentor's HDL Designer. It comes also with ...   Category :: Microprocessor Language :: VHDL License :: GPL Development status :: Alpha   SD/MMC Controller   Updated on: 13-Apr-2008   VLM: 1524 SD (Secure Digital) and MMC memory card controller with Wishbone slave interface. Handles all aspects of card initialization, 512 byte block read, and block write. Hides the complicated SD/MMC memory interface, and presents the user with a simple...   Category :: Communication controller Language :: Verilog License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   OpenRisc Development Board   Updated on: 03-May-2008   VLM: 763 Opensource OpenRisc Development Board. All CADsoft Eagle design files available to recreate the board using EagleLite, a freeware PCB design tool. Uses the largest Cyclone 2 device available in a QFP package, thus allowing larger RTL designs to b...   Category :: Prototype board Development status :: Production/Stable   Gator uProcessor - HC11 Compatible   Updated on: 04-Apr-2008   VLM: 319 Gator Microprocessor Overview * Motorola/Freescale 68xx Architecture * Source-code and machine-code compatible 68HC11 cpu core * Compatible with all HC11 C/C++ compilers including GNU GCC * Up to 100MHz operation in modern FPGAs * 2.5 t...   Category :: Microprocessor Language :: VHDL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable