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Development status :: Planning We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) 1 GigEthernet MAC core   Updated on: 20-Jan-2006   VLM: 311 Main Features IEEE 802.3-2002 compliant Supports only full duplex operations Supports full duplex flow control FCS generation for transmit, check for receiving packets. GMII interface to PHY layer and Simple application interface. Simple Ho...   Category :: Communication controller Language :: Verilog Development status :: Planning   6502VHDL   Updated on: 22-Dec-2003   VLM: 267 the goal of the project is to create a synthesizable core for the 6502 microprocessor. The initial target will be XILINX fpga devices. A prototype version will be running on the Digilent (digilentinc.com) spartan2E board.   Category :: Microprocessor Development status :: Planning   AES (Rijndael)   Updated on: 04-Dec-2002   VLM: 915 AES (Rijndael) is private key symmetric block cipher that can process data blocks of 128 bits, using cipher keys with lengths of 128, 192, 256 bits.   Category :: Crypto core Development status :: Planning   Audio DSP PCI Card   Updated on: 08-May-2006   VLM: 455 Target of this project is development FPGA and/or FPGA powered real time audio DSP applications. This is Free (like freedom) Hardware project, a PCI card with stand-alone possibility, with high-end digital and analog audio interfaces and MIDI.   Category :: Prototype board License :: LGPL Development status :: Planning   Constellation Encoder   Updated on: 07-Jan-2002   VLM: 148 The requirment of a constellation encoder is described in ITU-T G. 992.1. A cyclic redundancy check (CRC), scrambling, and forward error correction (FEC) coding shall be applied to the contents of data, and the data from the interleaved buffer ...   Category :: ECC core Development status :: Planning   E1 Framer/Deframer   Updated on: 04-May-2007   VLM: 254 CCITT G.704,G.706 E1 framer for 30 64kbps voice/data channel framing at 2.048 MHz bit rate.   Category :: Communication controller Language :: VHDL Development status :: Planning   Embedded 32-bit RISC uProcessor with SDRAM Controller   Updated on: 26-Jul-2002   VLM: 206 SOC with Embedded 32-bit mini RISC uProcessor and a SDRAM PC100 CL2 Controller. Five Stage RISC uProcessor 16MB SDRAM Space 2MB Flash Space DMA Bus Arbiter Serial-to-Parallel Converter PIO Interface Timer Watch-Dog Cache   Category :: SoC Development status :: Planning   FireWire (IEEE 1394)   Updated on: 01-Oct-2008   VLM: 450 FireWire, an Apple trademarked name for IEEE 1394 protocol, is a high performance serial bus protocol to provide easy-to-use, low-cost, high-speed communications   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Planning   Free-Standing O-O Processor   Updated on: 20-Mar-2007   VLM: 217 To design a free-standing, reentrant, parallelizable object-oriented processor.   Category :: Microprocessor Development status :: Planning   ham_7_4_enc   Updated on: 22-Jun-2004   VLM: 123 Hamming (7,4) encoder: This core encodes every 4-bit information into 7-bit codewords in such a way that any single-bit error can be corrected by the decoder.   Category :: ECC core Language :: Verilog Phaze :: Specification done Development status :: Planning   High Radix Montgomery RSA Crypto Core   Updated on: 14-Oct-2001   VLM: 174 RSA Cryptosystem is widely used in information technology. It encrypts and decrypts messages using public key mechanism. The security of this cryptosystem is based on the fact that it's very difficult to factorize large prime number.   Category :: Crypto core Development status :: Planning   HyperMTA   Updated on: 27-Apr-2002   VLM: 178 Super multithreaded architecture. VLIW Based core with many threads customizable to perform between 32 and 256 threads(estimated).   Category :: Microprocessor Development status :: Planning   IDEA core   Updated on: 03-Jul-2002   VLM: 146 The IDEA (International Data Encryption Algoritma) is a symetric-key block cipher that can encrypts 64-bits plaintexs to 64-bit ciphertexts using a 128-bit key, used for secure communications. It is also can do descryption with the same block ...   Category :: Crypto core Development status :: Planning   In System Programming via JTAG port   Updated on: 19-Jul-2008   VLM: 173 With a PC program, a JTAG cable, and a JTAG ciruit (realized in a cpld), you can program a memory chip, such as Flash or EEprom.   Category :: Other Language :: Verilog Development status :: Planning   LocationPU   Updated on: 06-Feb-2002   VLM: 145 This processor performs operations according to the memory positons the data is in. It has a smaller processor which runs threads. Threads only perform actions on pointers. These pointers move data from one position to another position to have...   Category :: Microprocessor Development status :: Planning   M2G - Media Oriented Systems Transport (MOST) IP core   Updated on: 17-Sep-2008   VLM: 265 With the M2G protocol a high performance, very scalable and easy to implement multi media transport system for in car use shall be defined. Inspired by the MOST protocol (Media Oriented Systems Transport) (http://www.mostcooperation.com) but with...   Category :: Communication controller Language :: Verilog Language :: VHDL Standard :: Wishbone compliant core Development status :: Planning   Matrix Implementation on a Linear Systolic Array   Updated on: 15-Oct-2007   VLM: 138 The project aims at implementing a 4 x 4 matrix implementation using a linear systolic array. This project could be used as the starting point for higher order scaling of the matrix and can be used as the start up design for performing various ot...   Category :: Coprocessor Language :: VHDL License :: GPL Development status :: Planning   MOST Network Interface Controller   Updated on: 25-Dec-2005   VLM: 185 Media Oriented Systems Transport is a multimedia fiber-optic network optimized for automotive applications. It is a network developed by the automotive industry for the automotive industry. Its design allows it to provide a low-overhead and low-c...   Category :: Communication controller Dependencies :: Technology Language :: Verilog Development status :: Planning   Multifunctional Advanced FPGA Architecture Personal Computer Board   Updated on: 21-Jun-2004   VLM: 237 This project is intended to design Personal Computer board, FPGA based, small ATX sized. This board will not have any hardware processor, only FPGA chip(s). ATX form factor, and de-facto "PC" standards for I/O features, will be respected.   Category :: Prototype board License :: LGPL Development status :: Planning   OCRP-2 board   Updated on: 15-Oct-2001   VLM: 158 penCores Reference Platform 2 (OCRP-2) is full-size length add-in PCI board. It includes two FPGA chips, video D/A and A/D converters, SDRAM memory, FLASH memory, PLD chip, USB, EIA232 and Ethernet PHY chips. It is designed for a debugging and ve...   Category :: Prototype board Development status :: Planning   OFDM modulator   Updated on: 15-Jul-2007   VLM: 273 OFDM modulator according to 802.11a standard. This model is describe in SystemC language.   Category :: Communication controller Language :: SystemC Development status :: Planning   Ogg Vorbis Encoder/Decoder for Virtex-II Pro   Updated on: 31-Mar-2004   VLM: 162 I am starting a project to implement an Ogg Vorbis Encoder or Decoder for the Xilinx Virtex-II Pro platform. I hope to take advantage of architecture specific items like block rams and multipliers. I'd like to target the XC2VP7 parts and progra...   Category :: Other Development status :: Planning   Open Design Prototype Board   Updated on: 07-Aug-2003   VLM: 437 The design of this CPLD board is intended to be an open design and to use free and open design tools in order to make it available to large number of designers around the world.   Category :: Prototype board Development status :: Planning   OPENCORES Application Board 1 (OAB1)   Updated on: 15-Oct-2001   VLM: 220 As you know, we have lots of free IP cores here, and we’ll have more coming soon. We have to use these cores otherwise they are invaluable. For this reason the idea of designing serials and open design boards are going to be available for any des...   Category :: Prototype board Development status :: Planning   RISC_Core_I   Updated on: 17-Jan-2002   VLM: 278 This is a 4 stage 16-Bit RISC processor system on chip designed for a Xilinx Virtex FPGA. RAM and ROM both are blockRAM based. Additionally, it is equiped with a parallel multiplier, a 8-Bit input and a 8-Bit output port. This core wasn't desig...   Category :: Microprocessor Development status :: Planning   ROSETTA Configurable Dot Matrix Display Controller   Updated on: 12-Jun-2006   VLM: 183 The ROSETTA Configurable Dot Matrix Display Controller core provides a modular expandable interface for any dimension displays build from LEDs dot matrix structures. This core can be configured for synthesis and P&R with any number of DM LEDs s...   Category :: Video controller Language :: Other Language :: Verilog Language :: VHDL License :: GPL Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Planning   RSA Processor   Updated on: 14-Oct-2001   VLM: 212 RSA ( Rivest Shamir Adleman )is crypthograph system that used to give a secret information and digital signature.   Category :: Crypto core Development status :: Planning   scARM - A SystemC ARM   Updated on: 28-Nov-2003   VLM: 456 SystemC Model of ARM and SystemC Model of AMBA(advanced microcontroller bus architecture)   Category :: Microprocessor Development status :: Planning   Smartcard interface (ISO7816-3)   Updated on: 26-Oct-2006   VLM: 188 Basic functionality for implementing a Smartcard. Sends and receives bytes. Sends an ATR (Answer to Reset) on reset. Interfaces with a layer that knows how to interpret commands via a Wishbone interface.   Category :: Communication controller Development status :: Planning   smbus_if   Updated on: 22-Jan-2004   VLM: 124 The System Management Bus (SMBus) is a two-wire interface through which simple system and power management related chips can communicate with the rest of a system. SMBus provides a control bus for system and power management related tasks. The SM...   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Planning   SONET/SDHframer   Updated on: 04-Mar-2003   VLM: 141 Want to work on creating IP for SONET/SDH framer/add-drop mux/mapper. Looking for a team who wants to start such a project.   Category :: Other Development status :: Planning   SpaceWire Interface   Updated on: 19-Sep-2008   VLM: 205 SpaceWire is a standard for high-speed links and networks, defined by the European Cooperation for Space Standardization ECSS-E50-12A standard. It is intended for use onboard spacecraft. This is a Wishbone compliant interface to SpaceWire netw...   Category :: Communication controller Language :: VHDL License :: GPL Standard :: Wishbone compliant core Development status :: Planning   SRT Division Unit   Updated on: 28-Aug-2007   VLM: 102 This is a planned collection of synthesizable hardware dividers at radix-2, radix-4, radix-16. All use the redundant number system for intermediary results to avoid the carry chain. All designs are fully parameteriseable and synthesizable. Th...   Category :: Library Language :: Verilog Development status :: Planning   tft lcd controller   Updated on: 24-Dec-2004   VLM: 438 The LCD controller is based on ARM Platform for Hitachi 7" LCD Panel 'tx18d16vm1caa'   Category :: Video controller Dependencies :: Technology Language :: Verilog License :: GPL Phaze :: FPGA proven Development status :: Planning   The Neptune Core   Updated on: 19-Feb-2006   VLM: 154 The Neptune core is an attempt to create a next-generation processor architecture that combines the best elements of register-based and stack-based designs.   Category :: Microprocessor Development status :: Planning   uAlpha - EV4 (DEC ) RISC easy implementation (uC)   Updated on: 28-Jan-2007   VLM: 190 The main idea of this project is to implement simple RISC processor with Alpha (EV4) instruction set.   Category :: Microprocessor Category :: SoC Language :: Verilog Language :: VHDL Development status :: Planning   wb_rtc   Updated on: 20-Sep-2003   VLM: 121 a real time clock IP core with wishbone bus compatible.   Category :: Other Development status :: Planning   wlan MAC CONTROLLER   Updated on: unknown   VLM: 198 WLAN is similar with LAN except that the medium containing data is via wireless .This project aims to design a MAC Controller based on IEEE 802.11B protocol.   Category :: Communication controller Development status :: Planning