By category :: Last updated :: Last created :: Most popular :: Best rated

Phaze :: ASIC proven We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) H.264/AVC Baseline Decoder   Updated on: 06-May-2008   VLM: 1066 This is a full dedicated H.264/AVC baseline decoder. Currently it supports QCIF 30fps decoding at 1.5MHz. It contains several main building blocks, such as bitstream parsing, intra-prediction, inter-prediction, and deblocking filter. It was both ...   Category :: Video controller Language :: Verilog Phaze :: ASIC proven Phaze :: FPGA proven Development status :: Production/Stable   I2C controller core   Updated on: 09-Aug-2008   VLM: 3155 I2C is a two-wire, bidirectional serials bus that provide a simple, efficient method of data exchange between devices.   Category :: Communication controller Language :: Verilog Language :: VHDL Phaze :: ASIC proven Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   OpenRISC 1000   Updated on: 20-Aug-2008   VLM: 11937 OpenRISC 1000 is an architecture of a family of open source, synthesizable RISC microprocessor cores. It is a 32-bit load and store RISC architecture designed with emphasis on speed, compact instruction set and scalability. OpenRISC 1000 targets ...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: ASIC proven Standard :: Wishbone compliant core Development status :: Production/Stable   TV80   Updated on: 24-Mar-2006   VLM: 461 The TV80 is a synthesizable 8-bit Z80-compatible microprocessor. It is a Verilog port of Daniel Wallner's T80, with some optimizations and a new verification environment. Documentation available on the web at http://ghutchis.googlepages.com/t...   Category :: Microprocessor Language :: Verilog Phaze :: ASIC proven Phaze :: FPGA proven Development status :: Mature Development status :: Production/Stable   VGA/LCD Controller   Updated on: 13-May-2004   VLM: 1536 The OpenCores VGA/LCD Controller core is a WISHBONE rev.B3 compliant embedded VGA core capable of driving CRT and LCD displays.   Category :: Video controller Language :: Verilog Phaze :: ASIC proven Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable