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License :: GPL We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) 1-bit Microprocessor   Updated on: 17-Oct-2006   VLM: 482 This project, in VHDL, implements a single-bit microprocessor based on the now obsolete Motorola MC14500B Industrial Control Unit. The ICU is basically a logic sequencer with a 4-bit instruction unit (16-instructions). In addition to the ICU, t...   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: Design done Development status :: Alpha   5x4Gbps CRC generator designed with standard cells   Updated on: 05-May-2004   VLM: 355 The design can handle 5 different channels at an input rate of 2Gbps each (the total output throughput is 5x4Gbps.) The generated CRCs are compatible with the 32-bit Ethernet standards. The circuit has been implemented with standard cells ...   Category :: Arithmetic core Language :: VHDL License :: GPL Development status :: Production/Stable   8b10b Encoder/Decoder   Updated on: 05-Oct-2006   VLM: 510 This project, written in generic synthesizable VHDL, provides two separate cores for encoding and decoding byte data according to the 8b/10b protocol. 8b/10b is widely used in high speed serial communication standards that need a run-length limit...   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: Design done Development status :: Production/Stable   ACEX 1K50 board   Updated on: 11-Sep-2004   VLM: 305 A prototyping board with ACEX 1K50, 128 KB SRAM, 512 KB Flash, serial driver and wtachdog.   Category :: Prototype board License :: GPL Phaze :: FPGA proven Development status :: Mature Development status :: Production/Stable   Adaptive LMS equalizer   Updated on: 25-Apr-2006   VLM: 367 This represent a VHDL implementation of PIPLINED architecture of ADAPTIVE LMS filter. and filter is demostrated to be used as equalizer for removing channel anomalies.   Category :: Communication controller Category :: DSP core Language :: VHDL License :: GPL Phaze :: Design done Development status :: Beta   baud generator   Updated on: 20-Dec-2007   VLM: 230 block to produce from a given clock frequency a baud rate clock and a x times baud rate enable pulse. Takes in a clock and an active high reset. Two outputs, both one clock wide active high. One at baud rate, one at x times baud rate. Param...   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   BigCounter   Updated on: 02-Jan-2008   VLM: 194 Uses the shift register technology to create a big counter, that gives out a pulse at the period specified as a generic.   Category :: Other Language :: VHDL License :: GPL Development status :: Beta   Camellia cores   Updated on: 23-Jun-2008   VLM: 185 VHDL implementations of Camellia cipher. All block size (128, 192, 256) are supported.   Category :: Crypto core Language :: VHDL License :: GPL Development status :: Beta   Color Converter   Updated on: 26-Feb-2007   VLM: 433 Here is universal high precision color converter component based on the direct 3x3 matrix multiplication (see our mult3x3 arithmetic core) without convert-specific (such as RGB<->YCbCr) optimization. The current color transformation is defined b...   Category :: Video controller Dependencies :: Other cores Language :: VHDL License :: LGPL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   Configurable Hamming Generator   Updated on: 21-Aug-2007   VLM: 226 This program automatically generates Hamming encoder and decoder for a given word width. It also generates a testbench to evaluate the generate modules.   Category :: ECC core Language :: VHDL License :: GPL Development status :: Production/Stable   cpu6502_tc   Updated on: 17-Apr-2008   VLM: 291 This is a VHDL IP core with True Cycle Timing for Rockwell's 6502 8-Bit CPU. With full functional input signals like ready, interrupt, non maskable interrupt and set overflow flag. Also available is the output signal sync which signals an op fetc...   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   cpu65c02_tc - 65C02 Processor Soft Core with accurate timing   Updated on: 12-Apr-2008   VLM: 195 The 65C02 is the upgraded version of the legendary R6502. cpu65c02_tc offers you an accurate timing for all new and upgraded op codes of the 65C02. This soft core was generated in VHDL and designed with Mentor's HDL Designer. It comes also with ...   Category :: Microprocessor Language :: VHDL License :: GPL Development status :: Alpha   Crypto-PAn   Updated on: 17-Feb-2007   VLM: 170 A hardware implementation of Prefix-Preserving IP Address Anonymization. The core makes use of a fully pipelined 128-bit AES (Rijndael) cipher engine as the underlying pseudorandom function, supports online key changes, and is capable of line rat...   Category :: Crypto core Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   DEFLATE   Updated on: 05-Jun-2006   VLM: 99 The deflate is a VHDL implementation of the popular DEFLATE algorithm for data compression. More information on DEFLATE and its implementation are available at the zlib home page http://www.zlib.net/zlib_docs.html   Language :: VHDL License :: GPL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Alpha   Dirac hardware implementation   Updated on: 05-Dec-2006   VLM: 133 A hardware implementation of the Dirac open source video codec. This codec uses motion compensation, wavelet transforms and arithmetic coding to achieve high coding performance.   License :: LGPL License :: GPL   External parallel port to internal wishbone master interface   Updated on: 26-Jun-2008   VLM: 227 This core is intended to be used as an interface between some functionality in an FPGA and an external microcontroller. The external microcontroller provides a simple 8bit interface to control some functions within the FPGA. These functions ar...   Category :: System controller Language :: VHDL License :: GPL Phaze :: Specification done Development status :: Alpha   FirGen/MultGen   Updated on: 28-Mar-2008   VLM: 404 VHDL core generator for FIR filters and Multiplier arrays with common input using "Nonrecursive Signed Common Subexpression Algorithm" for optimization program writen on C++ -------------------------- firgen [OPTION..] Aviable options ar...   Category :: DSP core Language :: Other Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   Fuzzy Logic Hardware Accelerator   Updated on: 07-Apr-2004   VLM: 182 This project is to design a Fuzzy Logic Hardware Accelerator (FLHA) that is WishBone compatible. FLHA is capable of generating fuzzy rule matrix and inference for it. The input and output data will be 64-bit. Each input and output data will have ...   Category :: Other Language :: VHDL License :: GPL Development status :: Beta   Gamepads   Updated on: 15-Sep-2005   VLM: 293 A collection of cores that interface to various gamepads.   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Beta   gsc   Updated on: 28-Aug-2007   VLM: 238 gnu systemc compiler - a systemc collection of tools, including a systemc to verilog translator.   Category :: Other Language :: SystemC Language :: Verilog License :: GPL Development status :: Beta Development status :: Production/Stable   Hardware looping unit   Updated on: 19-Oct-2006   VLM: 169 Tha main purpose of the hardware looping unit (HWLU) is to enhance program control units found in modern microprocessors, by efficiently handling loop increments and branches in nested loop structures. It is based on recently published work (deta...   Category :: Other Language :: VHDL License :: GPL Phaze :: Design done Development status :: Production/Stable   HiCoVec - a configurable SIMD CPU   Updated on: 06-Jun-2008   VLM: 262 The HiCoVec processor is based on a simple 32 bit scalar unit and connected with a vector unit for SIMD operations. The amount of data simultaneously processed in the vector unit can be configured as well as the amount of vector registers to h...   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Beta   I2S Interface   Updated on: 02-Feb-2008   VLM: 834 The I2S bus is an industry standard three-wire interface for streaming stereo audio between devices, typically between a cpu/dsp and a DAC/ADC. This core implements I2S transmitter and receiver.   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   I2S to Paralell ADC/DAC controller   Updated on: 20-Dec-2005   VLM: 297 This provides a bridge between a paralell device (such as a microcontroller (uC) and an I2C (!not! I2C) audio bus, generally used for ADC's and DAC's, such as in DVD & MP3 players   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Beta   IIE-PCI Board   Updated on: 06-Jul-2005   VLM: 322 The IIE-PCI Development Platform board is a low cost PCI device card with a programmable logic chip (Altera ACEX), dynamic ram, and expansion capabilities. The main purpose of the IIE-PCI board is to test PCI designs in a educational environme...   Category :: Prototype board Language :: Other License :: GPL Development status :: Production/Stable   Image warping/Texture mapping core   Updated on: 26-Jun-2008   VLM: 558 This core maps a texture to an object defined by a grid of control points.   Category :: Video controller Language :: Verilog License :: GPL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Beta   JOP: a Java Optimized Processor   Updated on: 24-Jul-2008   VLM: 1389 JOP is the implementation of the Java Virtual Machine (JVM) as concrete machine in hardware. The design is full synthesizable and fits in low-cost FPGA devices from Altera and Xilinx.   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   JPEG codec library based on microblaze   Updated on: 12-Mar-2008   VLM: 731 This is an open source JPEG codec, including both encoder and decoder, for embedded systems. It can be fully synthesized and implemented on FPGA. Different to a fully hardware implementation, this JPEG codec is designed based on Xilinx Microbl...   Category :: Video controller Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   keyboardcontroller   Updated on: 06-Jul-2005   VLM: 250 A simple keyboard controller that works by scanning a matrix. It requires the inputs to be pull-up high. After scanning the matrix and detecting a keypress-release it generates the corresponding translated set2 scancode. This controller also p...   Category :: Other Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   Lightweight 8080 compatible core   Updated on: 13-Nov-2007   VLM: 204 Small, microprogrammed 8080-compatible cpu core. Emphasis on area reduction and design simplicity.   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Alpha   M1 Core   Updated on: 14-Jul-2008   VLM: 748 The M1 Core is a 32-bit RISC CPU compatible with GCC. It is so simple that it can be used for didactical purposes.   Category :: Microprocessor Language :: Verilog License :: GPL Phaze :: Specification done Development status :: Beta   Matrix Implementation on a Linear Systolic Array   Updated on: 15-Oct-2007   VLM: 204 The project aims at implementing a 4 x 4 matrix implementation using a linear systolic array. This project could be used as the starting point for higher order scaling of the matrix and can be used as the start up design for performing various ot...   Category :: Coprocessor Language :: VHDL License :: GPL Development status :: Planning   McAdam's RISC Computer Architecture   Updated on: 02-Feb-2007   VLM: 202 marca is a simple 16-bit microprocessor, implementing a load/store instruction set architecture and featuring a 4-stage pipeline.   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   MCPU - A minimal CPU for a CPLD   Updated on: 21-Mar-2008   VLM: 812 mcpu is a minimal cpu designed to fit into a 32 macrocell CPLD. 4 Instructions and access to 64 bytes of memory are supported. Sourcecode is provided in VHDL and Verilog and occupies only a single printed page.   Category :: Microprocessor Language :: Verilog Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Mature Development status :: Production/Stable   nCore   Updated on: 28-Oct-2007   VLM: 250 This is a little-little processor core. It has 16 instructions. It is under developement again, since the latest version is deleted... It is not yet verified, tested, etc. but it's ready to compile.   Category :: Microprocessor Language :: Verilog License :: GPL Development status :: Alpha   NoCem -- Network on Chip emulator   Updated on: 12-Jul-2007   VLM: 229 A Network on Chip Emulation Tool, NoCem is a body of VHDL code configurable by a toplevel package file that can create a variety of Network on Chips on parameters of datawidth, virtual channel implementations, topology, and in-network buffering l...   Category :: SoC Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   oks8   Updated on: 24-Jan-2006   VLM: 185 oks8 is intended to provide a microcontroller in Verilog that like the KS86C4204/C4208/P4208 microcontroller (Samsung Inc.).   Category :: Microprocessor Language :: Verilog License :: GPL Standard :: Wishbone compliant core Development status :: Alpha   OPB PSRAM Controller   Updated on: 16-Feb-2008   VLM: 218 Memory Controller to acess a pseudo static ram in synchronous mode.   Category :: Memory core Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   OPB-compatible OneWire Master   Updated on: 09-Oct-2007   VLM: 195 This is a OneWire Master core that is fully compatible with the Xilinx OPB specification.   Category :: Communication controller Language :: Verilog License :: GPL Phaze :: Design done Phaze :: FPGA proven Development status :: Mature Development status :: Production/Stable   OPB-compatible VGA character display, no DAC   Updated on: 17-Oct-2007   VLM: 310 This is an OPB-compatible VGA character display for the Spartan 3E development board, which does not contain DACs. The core is very small, requiring only 3 BRAMs and 533 slices. All access is through write character commands, similar to an ...   Category :: Video controller Language :: Verilog License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   OpenRisc 1200 Graphic Configuration Tool   Updated on: 16-Sep-2005   VLM: 177 A Tcl/TK script to graphically configure OpenRisc 1200 microprocessor. Similar to LEON one.   Category :: Other Language :: Other License :: GPL Phaze :: Design done Development status :: Production/Stable   openVeriFLA - FPGA logic analyzer   Updated on: 03-Mar-2008   VLM: 314 No description provided   Category :: Library Language :: Verilog License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   PCI Board   Updated on: 20-Dec-2005   VLM: 452 A versatile small pci board project based on Spartan-II.   Category :: Prototype board License :: GPL Phaze :: Design done Development status :: Mature   Quadrature Decoder / Counter   Updated on: 23-Apr-2004   VLM: 402 Many devices use a process called quadrature to encode movement information. Use of two logic inputs can specify both direction and movement information reliably. This project is intended to provide a quick solution to those wishing to keep tra...   Category :: Communication controller Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   Raggedstone PCI Spartan-3 board   Updated on: 08-Feb-2007   VLM: 331 This page contains a port of the open pci core ported to Enterpoint's Raggedstone board. The project has been tested under the Linux and Windows versions of the Xilinx ISE. The project tarball includes a Makefile that will generate a working prom...   Category :: Prototype board Language :: Verilog Language :: VHDL License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Beta   Random Number Generator Library   Updated on: 14-Oct-2007   VLM: 343 A library of functions to generate random numbers with different distributions. The functions are intended for use in VHDL test benches where random data is required.   Category :: Library Language :: VHDL License :: GPL Phaze :: Design done Development status :: Production/Stable   rfid tag and reader   Updated on: 08-Nov-2006   VLM: 223 Verilog version of RFID tag model   Category :: SoC Language :: Verilog License :: GPL Development status :: Beta   ROSETTA Configurable Dot Matrix Display Controller   Updated on: 12-Jun-2006   VLM: 220 The ROSETTA Configurable Dot Matrix Display Controller core provides a modular expandable interface for any dimension displays build from LEDs dot matrix structures. This core can be configured for synthesis and P&R with any number of DM LEDs s...   Category :: Video controller Language :: Other Language :: Verilog Language :: VHDL License :: GPL Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Planning   S1 Core