By category :: Last updated :: Last created :: Most popular :: Best rated

License :: LGPL We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) 10_100_1000 Mbps tri-mode ethernet MAC   Updated on: 20-Mar-2008   VLM: 1031 10_100_1000 Mbps tri-mode ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed using less than 2000 LCs/LEs to implement full function. It will use inferred PADs to reduce technology dependancies. The wh...   Category :: Communication controller Language :: Verilog License :: LGPL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   ae18   Updated on: 11-Oct-2007   VLM: 248 A synthesizable core of the PIC18 cpu. It is capable of executing all PIC18 codes. It has been extensively simulated using Icarus Verilog 0.8.2 and GPLCVER 2.11a to confirm performance. The code is compiled using SDCC 2.5 and GPASM 0.13.4. Synthe...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   aeMB   Updated on: 11-May-2008   VLM: 860 A clean room implementation of an EDK3.2 binary compatible Microblaze processor core. It is FPGA proven and has been extensively simulated using Icarus Verilog 0.8.5 and GPLCVER 2.11a to confirm performance. Simulation code is compiled using GCC ...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   AES128   Updated on: 28-Dec-2004   VLM: 349 Advanced Encryption Standard Cryptographic Core   Category :: Crypto core Language :: VHDL License :: LGPL Phaze :: Design done Development status :: Production/Stable   Audio DSP PCI Card   Updated on: 08-May-2006   VLM: 88 Target of this project is development FPGA and/or FPGA powered real time audio DSP applications. This is Free (like freedom) Hardware project, a PCI card with stand-alone possibility, with high-end digital and analog audio interfaces and MIDI.   Category :: Prototype board License :: LGPL Development status :: Planning   Cache Model (Cycle Accurate) C++   Updated on: 30-Nov-2007   VLM: 8 This is a C++ implementation of a cache model. The controller does not mimic the exact states of an actual cache controller. Instead it just models the external interface and the internal model is optimized for simulation speed. This current mode...   License :: LGPL   Color Converter   Updated on: 26-Feb-2007   VLM: 390 Here is universal high precision color converter component based on the direct 3x3 matrix multiplication (see our mult3x3 arithmetic core) without convert-specific (such as RGB<->YCbCr) optimization. The current color transformation is defined b...   Category :: Video controller Dependencies :: Other cores Language :: VHDL License :: LGPL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   Dirac hardware implementation   Updated on: 05-Dec-2006   VLM: 73 A hardware implementation of the Dirac open source video codec. This codec uses motion compensation, wavelet transforms and arithmetic coding to achieve high coding performance.   License :: LGPL License :: GPL   HPC-16   Updated on: 08-Nov-2006   VLM: 60 Simple 16-bit microprocessor, 15-general purpose registers. custom instruction set, load-store RISC but current implementation non piplined, control unit hardwired, 64K address space, total 16-interrupts (10 maskable), memory mapped i/o. design w...   Category :: Microprocessor Language :: VHDL License :: LGPL Phaze :: Design done Development status :: Beta   I/Q Constellation diagram on VGA   Updated on: 02-Mar-2008   VLM: 58 Do you have I/Q digital waveforms in your system ? Do you want to have a quick look at them as a constellation but don't have access to a big lump of equipment ? This block takes in a stream of I/Q pairs, and outputs them in a VGA timing fo...   Category :: Video controller Language :: VHDL License :: LGPL Phaze :: Design done Development status :: Beta   JPEG Hardware Compressor   Updated on: 25-Feb-2008   VLM: 817 This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with resolution 352x288). Image resolution is...   Category :: Video controller Language :: VHDL License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable   LPC ROM emulator on USB dongle FPGA core set   Updated on: 30-Apr-2008   VLM: 973 This is ROM emulator/debugger hardware project in a USB dongle board format containing: Cyclone FPGA EP1C6T144C8N Serial Platform Flash Intel Strata Flash E28F128 (16MB) in 16 bit mode FTDI parallel to USB bridge FT245BM 4 segment LED displ...   Category :: Prototype board Category :: Communication controller Language :: VHDL License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable   miniMIPS   Updated on: 24-Mar-2006   VLM: 647 The miniMIPS is a 5 stage pipeline based on the MIPS I instruction set which is a 32 bits RISC architecture. Nearly all the instructions are supported with some custom feaures added. The core has been prototyped on an FPGA during an internship....   Category :: Microprocessor Language :: VHDL License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable   Monochrome Text-Mode VGA Video Display Adapter   Updated on: 09-Apr-2008   VLM: 531 This VHDL macro is a simple monochrome text-mode VGA Video Display Adapter (also referred to as video card). This kind of IP core, apart from to let you put text to the screen in your Pico/MicroBlaze SoC designs, may be useful (say) to debug inte...   Category :: Video controller Language :: VHDL License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable   Multifunctional Advanced FPGA Architecture Personal Computer Board   Updated on: 21-Jun-2004   VLM: 57 This project is intended to design Personal Computer board, FPGA based, small ATX sized. This board will not have any hardware processor, only FPGA chip(s). ATX form factor, and de-facto "PC" standards for I/O features, will be respected.   Category :: Prototype board License :: LGPL Development status :: Planning   OPB SPI Slave   Updated on: 15-May-2008   VLM: 376 The OPB SPI-Slave Core is full configurable and support DMA-Transfers to write or read data directly to a memory. The SPI-Slave receive/transmit Data to a SPI-Master, for example a DSP or processor. The SPI-Clock and OPB-Bus clocks are complete...   Category :: Communication controller Language :: VHDL License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable   OpenRISC 1000   Updated on: 14-May-2008   VLM: 12782 OpenRISC 1000 is an architecture of a family of open source, synthesizable RISC microprocessor cores. It is a 32-bit load and store RISC architecture designed with emphasis on speed, compact instruction set and scalability. OpenRISC 1000 targets ...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: ASIC proven Standard :: Wishbone compliant core Development status :: Production/Stable   PAL/NTSC encoder   Updated on: 10-Mar-2007   VLM: 594 PAL and NTSC encoders with internal carrier (DDS) and color burst generation. The core with 8 basic colours will fit into a small CPLD and needs rgb-signals, hsync,vsync and a 16/32 Mhz clock. Video output uses 5 resistors on a 75 Ohm load.   Category :: Video controller Language :: VHDL License :: LGPL Phaze :: Design done Development status :: Production/Stable   PCI Target   Updated on: 15-Feb-2008   VLM: 721 Simple PCI Target. PCI 32 bits. Whisbone compatible. Tested on Hardware (ALTERA/XILINX). Fits on small FPGA: About 200 LC's (ALTERA CYCLONE II).   Category :: System controller Language :: VHDL License :: LGPL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Production/Stable   SHA cores   Updated on: 20-May-2004   VLM: 71 This is a collection of SHA(Secure Hash Algorithm) IP cores.   Category :: Crypto core Language :: Verilog License :: LGPL Phaze :: Design done Development status :: Beta   SimpCon - a Simple SoC Interconnect   Updated on: 13-Nov-2007   VLM: 162 SimpCon is a specification for a simple and efficient system-on-chip (SoC) interconnect. SimpCon provides single cycle commands and provisions for pipelining of read and write connections. SimpCon is public domain and freely available. Transla...   Category :: SoC License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable   SPDIF Interface   Updated on: 14-Oct-2007   VLM: 493 An interface between the Wishbone bus and the SPDIF IEC958 "Digital audio interface". Separate transmitter and receiver. Dual sample buffers of configurable size. Access to channel status and subcode information. Configurable clocking.   Category :: Communication controller Language :: VHDL License :: LGPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   srl_fifo   Updated on: 28-Mar-2008   VLM: 198 a collection of fifo's , made out of srl's as found in Xilinx FPGA's. Small in depth, and synchronous only, but uses small amounts of an FPGA.   Category :: Memory core Language :: VHDL License :: LGPL Phaze :: Design done Development status :: Production/Stable   SystemC/Verilog MD5   Updated on: 15-Sep-2005   VLM: 178 A MD5 hash algorithm implementation in SystemC, including the equivalent synthesizable Verilog translation   Category :: Crypto core Language :: Other Language :: Verilog License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable   SystemC/Verilog Random Number Generator   Updated on: 20-Mar-2008   VLM: 260 A 32 bits random number generator based on the combination of a LFSR and a CASR, that gives very good statisticall properties   Category :: Other Language :: Other Language :: Verilog License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable   TG68 - execute 68000 Code   Updated on: 23-Jan-2008   VLM: 589 16/32 bit CPU for minimig   Category :: Microprocessor Language :: VHDL License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable   True matrix 3x3 multiplier   Updated on: 26-Feb-2007   VLM: 325 Here is the direct 3x3 matrix multiplication. Precision of matrix factors is 10-E4. Trnasform operations were verifyied by the comparing with Matlab's equation. Testbench is attached. Resource utilization by the core with 10-bit input data for...   Category :: Arithmetic core Language :: VHDL License :: LGPL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   Turbo Decoder   Updated on: 14-Jun-2005   VLM: 72 Double binary, DVB-RCS code, Soft Output Viterbi Algorithm, MyHDL model and testbench, synthesizable VHDL model   Category :: ECC core Language :: VHDL License :: LGPL Development status :: Beta   USB 1.1 Host and Function IP core   Updated on: 22-Mar-2008   VLM: 2117 USB 1.1 host and function modes of operation. Full (12Mbps) and low speed (1.5Mbps) operation. Isochronous data transfers supported. Function mode supports four endpoints.   Category :: Communication controller Language :: Verilog License :: LGPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   wb_ddr: Asynchronous DDR SDRAM controller   Updated on: 07-Jan-2008   VLM: 487 wb_ddr is a DDR SDRAM controller with a Wishbone bus interface written in VHDL. It was originally build to supprt the Xilinx Spartan3E Starter kit which includes a Spartan3E-500 FPGA and 64MB DDR266 RAM, but is known to support other FPGAs from X...   Category :: Memory core Language :: Verilog License :: LGPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   Wishbone BFM   Updated on: 21-Feb-2008   VLM: 80 VHDL reads a file of instructions to perform Wishbone access, as if it's a wishbone master. Used in testing a Wishbone peripheral with out having to instantiate and program a 'CPU' function.   Category :: Microprocessor Category :: SoC Language :: VHDL License :: LGPL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Beta   Wishbone LPC Host and Peripheral Bridge   Updated on: 15-Mar-2008   VLM: 244 Wishbone to Low-Pin-Count (LPC) bridge. Supports I/O Read/Write cycles, Memory Read/Write cycles, and Firmware Memory Read/Write cycles. Wishbone Slave to LPC Host, and LPC Peripheral to Wishbone Master modules are provided.   Category :: Communication controller Language :: Verilog License :: LGPL Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   wishbone out port from b3 spec   Updated on: 29-Jan-2008   VLM: 120 Rather cheeky this, but do you like me need a simple wishbone compliant thing to check your wishbone interface against. Well in the wishbone specification Appendix A, we have a bunch of such bits defined in VHDL. So thought I'd put them in...   Category :: SoC Language :: VHDL License :: LGPL Phaze :: Design done Standard :: Wishbone compliant core Development status :: Production/Stable   xmatchpro lossless data compressor   Updated on: 14-Jun-2007   VLM: 121 high-throughput parallel lossless data compressor/decompressor core   Category :: Other Language :: VHDL License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable   XTEA Crypto Core   Updated on: 14-Apr-2006   VLM: 110 This is a Verlog implementation of the XTEA encryption algorithm - see http://en.wikipedia.org/wiki/XTEA.   Category :: Crypto core Language :: Verilog License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable