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Category :: Memory core We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) CF Interleaver   Updated on: 08-May-2008   VLM: 181 Confluence generated memory interleavers.   Category :: Memory core Development status :: Production/Stable   DDR SDRAM Controller Core   Updated on: 09-Oct-2006   VLM: 1152 The DDR SDRAM Controller provides the user with a simplified interface to industry standard memory devices. Using this controller makes accesses to DDR SDRAM devices as simple as accesses to static RAM‘s. Initialization and auto refresh are au...   Category :: Memory core Development status :: Production/Stable   Generic FIFOs   Updated on: 11-Feb-2004   VLM: 694 Generic, multiple purpose, parameterizable FIFOs. Single and Dual Clock.   Category :: Memory core Language :: Verilog Phaze :: FPGA proven Development status :: Production/Stable   High Speed SDRAM Controller With Adaptive Bank Management and Command Pipeline   Updated on: 06-Mar-2008   VLM: 556 HSSDRC is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. The main features of HSSDRC IP core are: 1. Adaptive SDRAM bank control : command sequence is depending upon previous accesses to...   Category :: Memory core Language :: Other Phaze :: Design done Development status :: Alpha Development status :: Production/Stable   Memory cores   Updated on: 14-Oct-2001   VLM: 522 Contains: - Dualport port memory core - Single port memory core - Fifo buffer   Category :: Memory core Development status :: Production/Stable   Memory sizer   Updated on: 21-Dec-2001   VLM: 189 Automatically sizes memory accesses to fit different types of memory, dynamically. You may read/write DWORDS and WORDS using BYTE wide RAM, etc. Handles little endian and big endian, misaligned accesses etc. Resizable parameterized module. Wri...   Category :: Memory core Standard :: Wishbone compliant core Development status :: Production/Stable   OPB PSRAM Controller   Updated on: 16-Feb-2008   VLM: 165 Memory Controller to acess a pseudo static ram in synchronous mode.   Category :: Memory core Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable   Parameterisable DRAM model   Updated on: 27-Apr-2005   VLM: 263 Parameterisable DRAM model, i.e. scalable data and address widths. Simulation assertions can be toggled on/off. Uses !RAS/!CAS control sequence for modelling DRAM activity. Refresh is monitored with data corrupted to "UU ... "   Category :: Memory core Development status :: Production/Stable   Single Port ASRAM   Updated on: 17-Nov-2007   VLM: 222 The main purpose of this project was two-fold. The first purpose was to implement a client-server test architecture based on Bergeron's work in VHDL. The main advantage to this verification method is greater stress-test ability and removes the ne...   Category :: Memory core Development status :: Production/Stable   srl_fifo   Updated on: 28-Mar-2008   VLM: 238 a collection of fifo's , made out of srl's as found in Xilinx FPGA's. Small in depth, and synchronous only, but uses small amounts of an FPGA.   Category :: Memory core Language :: VHDL License :: LGPL Phaze :: Design done Development status :: Production/Stable   SSRAM interface   Updated on: 14-Oct-2001   VLM: 337 The 'SSRAM interface core' is a collection of designs for easy integration of synchronous srams (ZBT srams) in your designs.   Category :: Memory core Development status :: Beta   wb_ddr: Asynchronous DDR SDRAM controller   Updated on: 07-Jan-2008   VLM: 549 wb_ddr is a DDR SDRAM controller with a Wishbone bus interface written in VHDL. It was originally build to supprt the Xilinx Spartan3E Starter kit which includes a Spartan3E-500 FPGA and 64MB DDR266 RAM, but is known to support other FPGAs from X...   Category :: Memory core Language :: Verilog License :: LGPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   Wishbone FLASH Interface for Parallel FLASH   Updated on: 20-Jul-2008   VLM: 440 Wishbone FLASH Interface for Parallel FLASH (Intel StrataFlash.) Tested on the Xilinx Spartan3E Starter Kit.   Category :: Memory core Language :: Verilog License :: LGPL Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   ZBT SRAM WISHBONE controller   Updated on: 01-Aug-2008   VLM: 251 Interface to a pipelined ZBT SRAM chip, with several WISHBONE busses that share memory cycles.   Category :: Memory core Language :: Verilog License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Beta