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    By category :: Last updated :: Last created :: Most popular :: Best rated    

    Category :: DSP core

    We use a few icons to help identify projects:

      Indicates new project, that has been added in the last 30 days.
      Indicates project that is ready to use
      Indicates a WISHBONE Compliant Core

    VLM = Visits Last Month (how many people accessed project)
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    Adaptive LMS equalizer
     
    Updated on: 25-Apr-2006   VLM: 288
    This represent a VHDL implementation of PIPLINED architecture of ADAPTIVE LMS filter. and filter is demostrated to be used as equalizer for removing channel anomalies.   Category :: Communication controller
    Category :: DSP core
    Language :: VHDL
    License :: GPL
    Phaze :: Design done
    Development status :: Beta
    Top

     

    Biquad IIR Filter Core
     
    Updated on: 14-Oct-2001   VLM: 356
    IIR filter with two poles and two zeros.   Category :: DSP core
    Development status :: Production/Stable
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    CF FIR Filter
     
    Updated on: 08-May-2008   VLM: 294
    Confluence generated finite impulse response (FIR) filters.   Category :: DSP core
    Development status :: Production/Stable
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    Fast Hadamhard Transforms
     
    Updated on: 20-Apr-2007   VLM: 200
    The RTL code calculates the Fast Hadamhard transform(FHT) for a 8-bit input data. This has been coded as per the standard algorithm for FHT. It contains matrix elements addition and subtraction in a definite manner. The RTL code given here is syn...   Category :: DSP core
    Language :: Verilog
    Phaze :: Design done
    Development status :: Beta
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    FirGen/MultGen
     
    Updated on: 28-Mar-2008   VLM: 352
    VHDL core generator for FIR filters and Multiplier arrays with common input using "Nonrecursive Signed Common Subexpression Algorithm" for optimization program writen on C++ -------------------------- firgen [OPTION..] Aviable options ar...   Category :: DSP core
    Language :: Other
    Language :: VHDL
    License :: GPL
    Phaze :: FPGA proven
    Development status :: Production/Stable
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    Low Power FIR Filter
     
    Updated on: 29-Oct-2006   VLM: 440
    A fully programmable, 15-tap, FIR filter (written in VHDL), designed for low power consumption. Constructed at gate level to control architecture.   Category :: DSP core
    Development status :: Production/Stable
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