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Best rated projects We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core R = Rating (calculated from number of visits, downloads and activity) OpenRISC 1000   Updated on: 14-May-2008   R: 6854 OpenRISC 1000 is an architecture of a family of open source, synthesizable RISC microprocessor cores. It is a 32-bit load and store RISC architecture designed with emphasis on speed, compact instruction set and scalability. OpenRISC 1000 targets ...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: ASIC proven Standard :: Wishbone compliant core Development status :: Production/Stable   ZPU - the worlds smallest 32 bit CPU with GCC toolchain   Updated on: 09-May-2008   R: 2434 This is the worlds smallest 32 bit CPU with a GCC/GDB toolchain, operating systems support(eCos), simulator, etc. Multiple VHDL implementations available. BSD license, except for those pieces to the puzzle that already have another open so...   Category :: Microprocessor Language :: VHDL Phaze :: Design done Phaze :: FPGA proven Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   I2C controller core   Updated on: 09-Apr-2008   R: 2348 I2C is a two-wire, bidirectional serials bus that provide a simple, efficient method of data exchange between devices.   Category :: Communication controller Language :: Verilog Language :: VHDL Phaze :: ASIC proven Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   Ethernet MAC 10/100 Mbps   Updated on: 24-Sep-2007   R: 2095 The Ethernet MAC (Media Access Control), sublevel within the Data Link Layer of the OSI reference model. This core is designed for implementation of CSMA/CD LAN in accordance with the IEEE 802.3 standards. The MAC is the portion of ethernet core ...   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Production/Stable   Plasma - most MIPS I(TM) opcodes   Updated on: 02-May-2008   R: 1843 The Plasma CPU core supports interrupts and all MIPS I(TM) user mode instructions except unaligned load and store operations (which are patented) and exceptions.   Category :: Microprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   FPU   Updated on: 28-Apr-2007   R: 1468 The floating point unit (FPU) implemented during this project, is a 32-bit processing unit, which does arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard.   Category :: Arithmetic core Category :: Coprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   VGA/LCD Controller   Updated on: 13-May-2004   R: 1456 The OpenCores VGA/LCD Controller core is a WISHBONE rev.B3 compliant embedded VGA core capable of driving CRT and LCD displays.   Category :: Video controller Language :: Verilog Phaze :: ASIC proven Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   MCPU - A minimal CPU for a CPLD   Updated on: 21-Mar-2008   R: 1279 mcpu is a minimal cpu designed to fit into a 32 macrocell CPLD. 4 Instructions and access to 64 bytes of memory are supported. Sourcecode is provided in VHDL and Verilog and occupies only a single printed page.   Category :: Microprocessor Language :: Verilog Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Mature Development status :: Production/Stable   SD/MMC Controller   Updated on: 13-Apr-2008   R: 1189 SD (Secure Digital) and MMC memory card controller with Wishbone slave interface. Handles all aspects of card initialization, 512 byte block read, and block write. Hides the complicated SD/MMC memory interface, and presents the user with a simple...   Category :: Communication controller Language :: Verilog License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   Z80 System on Chip   Updated on: 16-May-2008   R: 1124 System on chip, based on T80 core. Version 0.5-DE1 is designed for Altera DE1 development board. Version 0.5-S3E is the port for Diligent Spartan 3E. Both projects provide access to leds, switches, buttons, keyboard and vga. DE1 version hav...   Category :: SoC Dependencies :: Other cores Language :: VHDL Development status :: Production/Stable   USB 1.1 Host and Function IP core   Updated on: 22-Mar-2008   R: 1114 USB 1.1 host and function modes of operation. Full (12Mbps) and low speed (1.5Mbps) operation. Isochronous data transfers supported. Function mode supports four endpoints.   Category :: Communication controller Language :: Verilog License :: LGPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   H.264/AVC Baseline Decoder   Updated on: 06-May-2008   R: 1112 This is a full dedicated H.264/AVC baseline decoder. Currently it supports QCIF 30fps decoding at 1.5MHz. It contains several main building blocks, such as bitstream parsing, intra-prediction, inter-prediction, and deblocking filter. It was both ...   Category :: Video controller Language :: Verilog Phaze :: ASIC proven Phaze :: FPGA proven Development status :: Production/Stable   DDR SDRAM Controller Core   Updated on: 09-Oct-2006   R: 1105 The DDR SDRAM Controller provides the user with a simplified interface to industry standard memory devices. Using this controller makes accesses to DDR SDRAM devices as simple as accesses to static RAM‘s. Initialization and auto refresh are au...   Category :: Memory core Development status :: Production/Stable   USB 2.0 Function Core   Updated on: 27-Jun-2005   R: 1067 USB 2.0 compliant core which allows data transfers of 480 Mb/s.   Category :: Communication controller Language :: Verilog Standard :: Wishbone compliant core Development status :: Production/Stable   Micro FPGA Board   Updated on: 15-Oct-2001   R: 987 Micro FPGA board is a stand alone, low cost, do-it-yourself board. All components are possible to get from a local electronics shop (with possible exception of Virtex part). Board includes one Xilinx Virtex XCV100 chip.   Category :: Prototype board Development status :: Production/Stable   PCI bridge   Updated on: 04-Jul-2006   R: 941 PCI bridge is a member of a family of open source cores. It is a bus bridge device, which enables access to PCI bus to other WISHBONE SoC bus compatible cores.   Category :: System controller Language :: Verilog Standard :: Wishbone compliant core Development status :: Production/Stable