AHB to Wishbone Bridge :: Overview
Project maintainers
Details
Name: ahb2wishbone
Created: Jul 31, 2007
Updated: Sep 7, 2007
SVN: Browse
Statistics: View
Other project properties
Category: SoC
Language: Verilog
Development status: Mature
Additional info:
Design done,
FPGA proven,
Specification done,
WishBone Compliant: Yes
License:
Features
- AHB 2.0 compliant
- Wishbone B.3 compliant
- AHB Burst NOT SUPPORTED
- Fully synthesisable
- Synchronous
- Verilog RTL
- Includes a Verilog Testbench with 10 Testcases