DragonBall/68K Wishbone interface :: Overview
Project maintainers
Details
Name: wbif_68k
Created: Dec 2, 2002
Updated: Feb 14, 2004
SVN: Browse
Statistics: View
Other project properties
Category: Other
Language: Verilog
Development status: Stable
Additional info:
Design done,
FPGA proven,
WishBone Compliant: Yes
License:
Description
This is a Motorola DragonBall/68K to Wishbone bridge. The core translates the 16bit DragonBall/68K bus into a full featured 16bit Wishbone master bus.
Features
- 16bit Motorola DragonBall/68K Interface
- 16bit full featured RevB.3 Wishbone Classic Master interface
- programmable address-bus size
- static synchronous design
- fully synthesisable
- 6LUTs in a Spartan-II, 32LCELLs in an ACEX