Viterbi HDL Code Generator :: Overview
Project maintainers
Details
Name: vhcg
Created: May 27, 2004
Updated: Apr 14, 2009
SVN: Browse
Statistics: View
Other project properties
Category: Arithmetic core
Language: Other
Development status: Beta
Additional info:
Design done,
WishBone Compliant: No
License: GPL
Features
- direct traceback option.
- self test automation
- support any popular convolution code.
- throughput and area of decoder are scalable.
- in place state metric storage.
- parameterized modules.
- something else.
Status
- Version 1.3
- Place a TD-SCDMA version of K=9 rate=1/2 decoder for download
- Place a VHDL version of K=9 rate=1/2 decoder for download, in the requirement of Mitchell.
- Version 1.2
- contributed by moti: add encoder.pl, new testbench, insert srst signal in traceback module
- Version 1.1
- Version 1.0
- To be continued
- Updated
Viterbi HDL Code Generator
This is a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions. I will be glad to head these Verilog HDL codes be used in some applications. If you have any advices, please email to jhonson.zhu@gmail.com. And I have creat a project at sourceforge.net, too. You can find them here. http://viterbi-gen.sourceforge.net Now you can post questions http://groups.yahoo.com/group/vhcg (Disabled)