Name: tg68
Created: Nov 26, 2007
Updated: Feb 10, 2009
SVN: Browse
Statistics: View
Category: Processor
Language: VHDL
Development status: Stable
Additional info:
FPGA proven,
WishBone Compliant: No
License: LGPL
This is a stable Version of a 68000 compatible CPU.
It is an adapted Version to use with the Minimig Core.
"compatible" means that most of byte and word Instructions are cycle exact but many other Instructions are faster.
"adapted" means that the synchronous Mode, some bus control signals and the FC Out are missing. They are not needed for the minimig.
Tested with the Dennis van Weeren Minimig Core on the C-One Board with FPGA Extender from Individual Computers.
Source Code and Bitstreamfiles here:
http://c64upgra.de/c-one/
latest bugfix:
10.feb.2009 shift and rotation opcode
21.jan.2009 insert missing RTR opcode