SimpCon - a Simple SoC Interconnect :: Overview
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Details
Name: simpcon
Created: Nov 28, 2005
Updated: Nov 13, 2007
SVN: Browse
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Other project properties
Category: SoC
Language:
Development status: Stable
Additional info:
FPGA proven,
WishBone Compliant: No
License: LGPL
Description
SimpCon is a specification for a simple and efficient system-on-chip (SoC) interconnect. SimpCon provides single cycle commands and provisions for pipelining of read and write connections. SimpCon is public domain and freely available.
Translation to and from Wishbone, the opencores standard interface, are provided.
Documentation is in the CVS at http://www.opencores.org/cvsweb.cgi/~checkout~/simpcon/doc/simpcon.pdf
A paper published at the Austrochip on SimpCon is available from:
http://www.jopdesign.com/doc/simpcon_austrochip2007.pdf
Features
- Synchronous interface
- Master/Slave connection
- Piplined transactions
- Low resource usage
- Simple to implement
Status
- First draft document written
- Master implemented for JOP in Cyclone and Spartan-3
- Slave for SRAM access (read pipeline level 2)
- JOP IO devices connected as SimpCon slaves
- Wishbone/SimpCon bridge available