SystemC to Verilog Synthesizable Subset Translator :: Overview
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Details
Name: sc2v
Created: Oct 8, 2004
Updated: Mar 19, 2007
SVN: Browse
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Other project properties
Category: Other
Language:
Development status: Stable
Additional info:
Design done,
WishBone Compliant: No
License:
Description
The sc2v translator is a software tool that translates a SystemC RT description into a Verilog equivalent one.
The sc2v translator is based on lex and yacc tools.
You need lex and yacc installed in order to compile sc2v.
This work is given by Universidad Rey Juan Carlos (Spain)
www.escet.urjc.es/~jmartine