PIF2WB :: Overview
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Details
Name: pif2wb
Created: Aug 4, 2007
Updated: Aug 7, 2007
SVN: Browse
Statistics: View
Other project properties
Category: SoC
Language: VHDL
Development status: Beta
Additional info:
Design done,
Specification done,
WishBone Compliant: Yes
License:
Description
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
Features
- PIF master support
- Wishbone slave support
- Burst transfers support
- VHDL RTL
- Fully synthesisable